Mnemonic

Symbolic
Operation

Flags
S Z H P/V N C

Opcode
76 543 210

Hex

Bytes

M
Cycles

Clock
Cycles

Comments

LD r, r

r r

01 r r   

1

1

4

r, r Reg
000 B
001 C
010 D
011 E
100 H
101 L
111 A

LD r, n

r n

00 r 110
n

2

2

7

LD r, (HL)

r (HL)

01 r 110

1

2

7

LD r, (IX + d)

r (IX + d)

11 011 101
01 r 110
d

DD

3

5

19

LD r, (IY + d)

r (IY + d)

11 111 101
01 r 110
d

FD

3

5

19

LD (HL), r

(HL) r

01 110 r

1

2

7

LD (IX + d), r

(IX + d) r

11 011 101
01 110 r
d

DD

3

5

19

LD (IY + d), r

(IY + d) r

11 111 101
01 110 r
d

FD

3

5

19

LD (HL), n

(HL) n

00 110 110
n

36

2

3

10

LD (IX + d), n

(IX + d) n

11 011 101
00 110 110
d
n

DD
36

4

5

19

LD (IY + d), n

(IY + d) n

11 111 101
00 110 110
d
n

FD
36

4

5

19

LD A, (BC)

A (BC)

00 001 010

0A

1

2

7

LD A, (DE)

A (DE)

00 011 010

1A

1

2

7

LD A, (nn)

A (nn)

00 111 010
n
n

3A

3

4

13

LD (BC), A

(BC) A

00 000 010

02

1

2

7

LD (DE), A

(DE) A

00 010 010

12

1

2

7

LD (nn), A

(nn) A

00 110 010
n
n

32

3

4

13

Notes:

r, r means any of the registers A, B, C, D, E, H, L.

Flag Notation:

= flag is not affected.

Mnemonic

Symbolic
Operation

Flags
S    Z    H   P/V  N    C

Opcode
76 543 210

Hex

Bytes

M
Cycles

Clock
Cycles

Comments

LD dd, nn

dd ¬ nn

•     •     •     •     •     • 

00 dd0 001
¬    n     ®
¬    n     ®

3

3

10

dd     Pair
00     BC
01     DE
10     HL
11     SP

LD IX, nn

IX ¬ nn

•     •     •     •     •     • 

11 011 101
00 100 001
¬     n     ®
¬     n     ®

DD
21

4

4

14

LD IY, nn

IY ¬ nn

•     •     •     •     •     • 

11 111 101
00 100 001
¬    n     ®
¬    n     ®

FD
21

4

4

14

LD HL, (nn)

L ¬ (nn)
H ¬ (nn+1)

•     •     •     •     •     • 

00 101 010
¬    n     ®
¬    n     ®

2A

3

5

16

LD dd, (nn)

dd_L ¬ (nn)
dd_H ¬ (nn+1)

•     •     •     •     •     • 

11 101 101
01 dd1 011
¬    n     ®
¬    n     ®

ED

4

6

20

LD IX, (nn)

IX_L ¬ (nn)
IX_H ¬ (nn+1)

•     •     •     •     •     • 

11 011 101
00 101 010
¬    n     ®
¬    n     ®

DD
2A

4

6

20

LD IY, (nn)

IY_L ¬ (nn)
IY_H ¬ (nn+1)

•     •     •     •     •     • 

11 111 101
00 101 010
¬    n     ®
¬    n     ®

FD
2A

4

6

20

LD (nn), HL

(nn) ¬ L
(nn+1) ¬ H

•     •     •     •     •     • 

00 100 010
¬    n     ®
¬    n     ®

22

3

5

16

LD (nn), dd

(nn) ¬ dd_L
(nn+1) ¬ dd_H

•     •     •     •     •     • 

11 101 101
01 dd0 011
¬    n     ®
¬    n     ®

DD

4

6

20

LD (nn), IX

(nn) ¬ IX_L
(nn+1) ¬ IX_H

•     •     •     •     •     • 

11 011 101
00 100 010
¬    n     ®
¬    n     ®

DD
22

4

6

20

LD (nn), IY

(nn) ¬ IY_L
(nn+1) ¬ IY_H

•     •     •     •     •     • 

11 111 101
00 100 010
¬    n     ®
¬    n     ®

FD
22

4

6

20

LD SP, HL

SP ¬ HL

•     •     •     •     •     • 

11 111 001

F9

1

1

6

LD SP, IX

SP ¬ IX

•     •     •     •     •     • 

11 011 101
11 111 001

DD
F9

2

2

10

LD SP, IY

SP ¬ IY

•     •     •     •     •     • 

11 111 101
11 111 001

FD
F9

2

2

10

EX DE,HL

DE « HL

•     •     •     •     •     • 

11 101 011

EB

1

1

4

EX (SP), HL

H « (SP+1)
L « (SP)

•     •     •     •     •     • 

11 100 011

E3

1

5

19

PUSH qq

SP ¬ SP - 1
(SP) ¬ qq_H
SP ¬ SP - 1
(SP) ¬ qq_L

•     •     •     •     •     • 

11 qq0 101

1

3

11

qq     Pair
00     BC
01     DE
10     HL
11     AF

PUSH IX

SP ¬ SP - 1
(SP) ¬ IX_H
SP ¬ SP - 1
(SP) ¬ IX_L

•     •     •     •     •     • 

11 011 101
11 100 101

DD
E5

2

4

15

PUSH IY

SP ¬ SP - 1
(SP) ¬ IY_H
SP ¬ SP - 1
(SP) ¬ IY_L

•     •     •     •     •     • 

11 111 101
11 100 101

FD
E5

2

4

15

POP qq

qq_L ¬ (SP)
SP ¬ SP + 1
qq_H ¬ (SP)
SP ¬ SP + 1

•     •     •     •     •     • 

11 qq0 001

1

3

10

POP IX

IX_L ¬ (SP)
SP ¬ SP + 1
IX_H ¬ (SP)
SP ¬ SP + 1

•     •     •     •     •     • 

11 011 101
11 100 001

DD
E1

2

4

14

POP IY

IY_L ¬ (SP)
SP ¬ SP + 1
IY_H ¬ (SP)
SP ¬ SP + 1

•     •     •     •     •     • 

11 111 101
11 100 001

FD
E1

2

4

14

Notes:

dd is any of the register pair BC, DE, HL, SP.
qq is any of the register pair BC, DE, HL, AF.

Flag Notation:

• = flag is not affected.

Mnemonic

Symbolic
Operation

Flags
S    Z    H   P/V  N    C

Opcode
76 543 210

Hex

Bytes

M
Cycles

Clock
Cycles

Comments

ADD A, r

A ¬ A + r

↕    ↕    ↕    V    0    ↕

10 000   r   

1

1

4

r        Reg
000   B
001   C
010   D
011   E
100   H
101   L
111   A

ADD A, n

A ¬ A + n

↕    ↕    ↕    V    0    ↕

11 000 110
¬    n     ®

2

2

7

ADD A, (HL)

A ¬ A + (HL)

↕    ↕    ↕    V    0    ↕

10 000 110

1

2

7

ADD A, (IX + d)

A ¬ A + (IX + d)

↕    ↕    ↕    V    0    ↕

11 011 101
10 000 110
¬    d     ®

DD

3

5

19

ADD A, (IY + d)

A ¬ A + (IY + d)

↕    ↕    ↕    V    0    ↕

11 111 101
10 000 110
¬    d     ®

FD

3

5

19

ADC A, r

A ¬ A + r + CY

↕    ↕    ↕    V    0    ↕

10 001   r   

1

1

4

ADC A, n

A ¬ A + n + CY

↕    ↕    ↕    V    0    ↕

11 001 110
¬    n     ®

2

2

7

ADC A, (HL)

A ¬ A + (HL) + CY

↕    ↕    ↕    V    0    ↕

10 001 110

1

2

7

ADC A, (IX + d)

A ¬ A + (IX + d) + CY

↕    ↕    ↕    V    0    ↕

11 011 101
10 001 110
¬    d     ®

DD

3

5

19

ADC A, (IY + d)

A ¬ A + (IY + d) + CY

↕    ↕    ↕    V    0    ↕

11 111 101
10 001 110
¬    d     ®

FD

3

5

19

SUB r

A ¬ A - r

↕    ↕    ↕    V    1    ↕

10 010   r   

1

1

4

SUB n

A ¬ A - n

↕    ↕    ↕    V    1    ↕

11 010 110
¬    n     ®

2

2

7

SUB (HL)

A ¬ A - (HL)

↕    ↕    ↕    V    1    ↕

10 010 110

1

2

7

SUB (IX + d)

A ¬ A - (IX + d)

↕    ↕    ↕    V    1    ↕

11 011 101
10 010 110
¬    d     ®

DD

3

5

19

SUB (IY + d)

A ¬ A - (IY + d)

↕    ↕    ↕    V    1    ↕

11 111 101
10 010 110
¬    d     ®

FD

3

5

19

SBC A, r

A ¬ A - r - CY

↕    ↕    ↕    V    1    ↕

10 011   r   

1

1

4

SBC A, n

A ¬ A - n - CY

↕    ↕    ↕    V    1    ↕

11 011 110
¬    n     ®

2

2

7

SBC A, (HL)

A ¬ A - (HL) - CY

↕    ↕    ↕    V    1    ↕

10 011 110

1

2

7

SBC A, (IX + d)

A ¬ A - (IX + d) - CY

↕    ↕    ↕    V    1    ↕

11 011 101
10 011 110
¬    d     ®

DD

3

5

19

SBC A, (IY + d)

A ¬ A - (IY + d) - CY

↕    ↕    ↕    V    1    ↕

11 111 101
10 011 110
¬    d     ®

FD

3

5

19

CP r

A - r

↕    ↕    ↕    V    1    ↕

10 111   r   

1

1

4

CP n

A - n

↕    ↕    ↕    V    1    ↕

11 111 110
¬    n     ®

2

2

7

CP (HL)

A - (HL)

↕    ↕    ↕    V    1    ↕

10 111 110

1

2

7

CP (IX + d)

A - (IX + d)

↕    ↕    ↕    V    1    ↕

11 011 101
10 111 110
¬    d     ®

DD

3

5

19

CP (IY + d)

A - (IY + d)

↕    ↕    ↕    V    1    ↕

11 111 101
10 111 110
¬    d     ®

FD

3

5

19

AND r

A ¬ A and r

↕    ↕    1    P    0    0

10 100   r   

1

1

4

AND n

A ¬ A and n

↕    ↕    1    P    0    0

11 100 110
¬    n     ®

2

2

7

AND (HL)

A ¬ A and (HL)

↕    ↕    1    P    0    0

10 100 110

1

2

7

AND (IX + d)

A ¬ A and (IX + d)

↕    ↕    1    P    0    0

11 011 101
10 100 110
¬    d     ®

DD

3

5

19

AND (IY + d)

A ¬ A and (IY + d)

↕    ↕    1    P    0    0

11 111 101
10 100 110
¬    d     ®

FD

3

5

19

OR r

A ¬ A or r

↕    ↕    1    P    0    0

10 110   r   

1

1

4

OR n

A ¬ A or n

↕    ↕    1    P    0    0

11 110 110
¬    n     ®

2

2

7

OR (HL)

A ¬ A or (HL)

↕    ↕    1    P    0    0

10 110 110

1

2

7

OR (IX + d)

A ¬ A or (IX + d)

↕    ↕    1    P    0    0

11 011 101
10 110 110
¬    d     ®

DD

3

5

19

OR (IY + d)

A ¬ A or (IY + d)

↕    ↕    1    P    0    0

11 111 101
10 110 110
¬    d     ®

FD

3

5

19

XOR r

A ¬ A xor r

↕    ↕    1    P    0    0

10 101   r   

1

1

4

XOR n

A ¬ A xor n

↕    ↕    1    P    0    0

11 101 110
¬    n     ®

2

2

7

XOR (HL)

A ¬ A xor (HL)

↕    ↕    1    P    0    0

10 101 110

1

2

7

XOR (IX + d)

A ¬ A xor (IX + d)

↕    ↕    1    P    0    0

11 011 101
10 101 110
¬    d     ®

DD

3

5

19

XOR (IY + d)

A ¬ A xor (IY + d)

↕    ↕    1    P    0    0

11 111 101
10 101 110
¬    d     ®

FD

3

5

19

INC r

r ¬ r + 1

↕    ↕    ↕    V    0    •

00   r    100

1

1

4

INC (HL)

(HL) ¬ (HL) + 1

↕    ↕    ↕    V    0    •

00 110 100

1

3

11

INC (IX + d)

(IX + d) ¬ (IX + d) + 1

↕    ↕    ↕    V    0    •

11 011 101
00 110 100
¬    d     ®

DD

3

6

23

INC (IY + d)

(IY + d) ¬ (IY + d) + 1

↕    ↕    ↕    V    0    •

11 111 101
00 110 100
¬    d     ®

FD

3

6

23

DEC r

r ¬ r - 1

↕    ↕    ↕    V    1    •

00   r    101

1

1

4

DEC (HL)

(HL) ¬ (HL) - 1

↕    ↕    ↕    V    1    •

00 110 101

1

3

11

DEC (IX + d)

(IX + d) ¬ (IX + d) -1

↕    ↕    ↕    V    1    •

11 011 101
00 110 101
¬    d     ®

DD

3

6

23

DEC (IY + d)

(IY + d) ¬ (IY + d) - 1

↕    ↕    ↕    V    1    •

11 111 101
00 110 101
¬    d     ®

FD

3

6

23

DAA

Converts Accumulator contents into packed BCD, following add or subtract with packed BCD operands

↕    ↕    ↕    P    •    ↕

00 100 111

27

1

1

4

CPL

        _
A ¬ A

•     •     1    •     1    •

00 101 111

2F

1

1

4

One’s complement.

NEG

        _
A ¬ A  + 1

↕    ↕    ↕    V    1    ↕

11 101 101
01 000 100

ED
44

2

2

8

Two’s complement.

Notes:

The V symbol in the P/V flag column indicates that the P/V flag contains the overflow of the operation.
Similarly the P symbol indicates parity.
r means any of the registers A, B, C, D, E, H, L.
CY means the carry flip-flop.

Flag Notation:

• = flag is not affected, 0 = flag is reset, 1 = flag is set,
↕ = flag is set according to the result of the operation.

Mnemonic

Symbolic
Operation

Flags
S    Z    H   P/V  N    C

Opcode
76 543 210

Hex

Bytes

M
Cycles

Clock
Cycles

Comments

ADD HL, ss

HL ¬ HL + ss

•     •     ↕²   •     0    ↕¹

00 ss1 001

1

3

11

ss     Reg.
00     BC
01     DE
10     HL
11     SP

pp     Reg.
00     BC
01     DE
10        IX
11        SP

rr      Reg.
00     BC
01        DE
10     IY
11     SP

ADC HL, ss

HL ¬ HL + ss + CY

↕¹   ↕¹   ↕²   V¹  0    ↕¹

11 101 101
01 ss1 010

ED

2

4

15

SBC HL, ss

HL ¬ HL – ss –  CY

↕¹   ↕¹   ↕²   V¹  1    ↕¹

11 101 101
01 ss0 010

ED

2

4

15

ADD IX, pp

IX ¬ IX + pp

•     •     ↕²   •     0    ↕¹

11 011 101
00 pp1 001

DD

2

4

15

ADD IY, rr

IY ¬ IY + rr

•     •     ↕²   •     0    ↕¹

11 111 101
00  rr1  001

FD

2

4

15

INC ss

ss ¬ ss + 1

•     •     •     •     •     •

00 ss0 011

1

1

6

INC IX

IX ¬ IX + 1

•     •     •     •     •     •

11 011 101
00 100 011

DD
23

2

2

10

INC IY

IY ¬ IY + 1

•     •     •     •     •     •

11 111 101
00 100 011

FD
23

2

2

10

DEC ss

ss ¬ ss - 1

•     •     •     •     •     •

00 ss1 011

1

1

6

DEC IX

IX ¬ IX - 1

•     •     •     •     •     •

11 011 101
00 101 011

DD
2B

2

2

10

DEC IY

IY ¬ IY - 1

•     •     •     •     •     •

11 111 101
00 101 011

FD
2B

2

2

10

Notes:

The V symbol in the P/V flag column indicates that the P/V flag contains the overflow of the operation.
Ss means any of the registers BC, DE, HL, SP.
Pp means any of the registers BC, DE, IX, SP.
Rr means any of the registers BC, DE, IY, SP.
16 bit additions are performed by first adding the two low order eight bits, and then the two high order eight bits.
¹  Indicates the flag is affected by the 16 bit result of the operation.
²  Indicates the flag is affected by the 8 bit addition of the high order eight bits.
CY means the carry flip-flop.

Flag Notation:

• = flag is not affected, 0 = flag is reset, 1 = flag is set,
↕ = flag is set according to the result of the operation.

Mnemonic

Symbolic
Operation

Flags
S    Z    H   P/V  N    C

Opcode
76 543 210

Hex

Bytes

M
Cycles

Clock
Cycles

Comments

CCF

          ___
CY ¬ CY

•     •     X    •     0    ↕

00 111 111

3F

1

1

4

Complement
carry flag.

SCF

CY ¬ 1

•     •     0    •     0    1

00 110 111

37

1

1

4

NOP

No Operation

•     •     •     •     •     •

00 000 000

00

1

1

4

HALT

CPU halted

•     •     •     •     •     •

01 110 110

76

1

1

4

DI¹

IFF ¬ 0

•     •     •     •     •     •

11 110 011

F3

1

1

4

EI¹

IFF ¬ 1

•     •     •     •     •     •

11 111 011

FB

1

1

4

Notes:

The V symbol in the P/V flag column indicates that the P/V flag contains the overflow of the operation.
Similarly the P symbol indicates parity.
¹    No interrupts are issued directly after a DI or EI.
CY means the carry flag.

Flag Notation:

• = flag is not affected, 0 = flag is reset, 1 = flag is set, X = flag is “unknown”,
↕ = flag is set according to the result of the operation.

Mnemonic

Symbolic
Operation

Flags
S    Z    H   P/V  N    C

Opcode
76 543 210

Hex

Bytes

M
Cycles

Clock
Cycles

Comments

JP nn

PC ¬ nn

•      •     •     •     •     •

11 000 011
¬    n     ®
¬    n     ®

C3

3

3

10

JP cc, nn

if cc is true,
PC ¬ nn

•      •     •     •     •     •

11  cc  010
¬    n     ®
¬    n     ®

3

3

10

cc     Condition
000   NZ non zero
001   Z  zero
010   NC non carry
011   C carry
100   PO parity odd
101   PE parity even
110   P sign positive
111   M sign negative

JP ( HL )

PC ¬ HL

•      •     •     •     •     •

11 101 001

E9

1

1

4

JP ( IX )

PC ¬ IX

•      •     •     •     •     •

11 011 101
11 101 001

DD
E9

2

2

8

JP ( IY )

PC ¬ IY

•      •     •     •     •     •

11 111 101
11 101 001

FD
E9

2

2

8

Flag Notation:

• = flag is not affected.

Mnemonic

Symbolic
Operation

Flags
S    Z    H   P/V  N    C

Opcode
76 543 210

Hex

Bytes

M
Cycles

Clock
Cycles

Comments

CALL nn

SP ¬ SP - 1
(SP) ¬ PC_H
SP ¬ SP - 1
(SP) ¬ PC_L
PC ¬ nn

•     •     •     •     •     •

11 001 101
¬    n     ®
¬    n     ®

CD

3

5

17

CALL cc, nn

if cc is true,
SP ¬ SP - 1
(SP) ¬ PC_H
SP ¬ SP - 1
(SP) ¬ PC_L
PC ¬ nn

•     •     •     •     •     •

11 cc  100
¬    n     ®
¬    n     ®

3
3

3
5

10
17

if cc is false
if cc is true

cc     Condition
000   NZ non zero
001   Z  zero
010   NC non carry
011   C carry
100   PO parity odd
101   PE parity even
110   P sign positive
111   M sign negative

RET

PC_L ¬ (SP)
SP ¬ SP + 1
PC_H ¬ (SP)
SP ¬ SP + 1

•     •     •     •     •     •

11 001 001

C9

1

3

10

RET cc

if cc is true,
PC_L ¬ (SP)
SP ¬ SP + 1
PC_H ¬ (SP)
SP ¬ SP + 1

•     •     •     •     •     •

11 cc  000

1
1

1
3

5
11

if cc is false
if cc is true

RST p

SP ¬ SP - 1
(SP) ¬ PC_H
SP ¬ SP - 1
(SP) ¬ PC_L
PC ¬ p

•     •     •     •     •     •

11   t   111

1

3

11

_t_    __p__
000   0000h
001   0008h
010   0010h
011   0018h
100   0020h
101   0028h
110   0030h
111   0038h

Flag Notation:

• = flag is not affected.

Mnemonic

Symbolic
Operation

Flags
S    Z    H   P/V  N    C

Opcode
76 543 210

Hex

Bytes

M
Cycles

Clock
Cycles

Comments

RLCA

•     •     0    •     0    ↕

00 000 111

07

1

1

4

RLA

•     •     0    •     0    ↕

00 010 111

17

1

1

4

RRCA

•     •     0    •     0    ↕

00 001 111

0F

1

1

4

RRA

•     •     0    •     0    ↕

00 011 111

1F

1

1

4

RLC r

↕    ↕    0    P    0    ↕

11 001 011
00 000   r   

CB

2

2

8

r        Reg
000   B
001   C
010   D
011   E
100   H
101   L
111   A

RLC (HL)

↕    ↕    0    P    0    ↕

11 001 011
00 000 110

CB

2

4

15

RLC (IX + d)

↕    ↕    0    P    0    ↕

11 011 101
11 001 011
¬    d    ®
00 000 110

DD
CB

4

6

23

RLC (IY + d)

↕    ↕    0    P    0    ↕

11 111 101
11 001 011
¬    d    ®
00 000 110

FD
CB

4

6

23

RL r

↕    ↕    0    P    0    ↕

11 001 011
00 010   r   

CB

2

2

8

RL (HL)

↕    ↕    0    P    0    ↕

11 001 011
00 010 110

CB

2

4

15

RL (IX + d)

↕    ↕    0    P    0    ↕

11 011 101
11 001 011
¬    d    ®
00 010 110

DD
CB

4

6

23

RL (IY + d)

↕    ↕    0    P    0    ↕

11 111 101
11 001 011
¬    d    ®
00 010 110

FD
CB

4

6

23

RRC r

↕    ↕    0    P    0    ↕

11 001 011
00 001   r   

CB

2

2

8

RRC (HL)

↕    ↕    0    P    0    ↕

11 001 011
00 001 110

CB

2

4

15

RRC (IX + d)

↕    ↕    0    P    0    ↕

11 011 101
11 001 011
¬    d    ®
00 001 110

DD
CB

4

6

23

RRC (IY + d)

↕    ↕    0    P    0    ↕

11 111 101
11 001 011
¬    d    ®
00 001 110

FD
CB

4

6

23

RR r

↕    ↕    0    P    0    ↕

11 001 011
00 011  r   

CB

2

2

8

RR (HL)

↕    ↕    0    P    0    ↕

11 001 011
00 011 110

CB

2

4

15

RR (IX + d)

↕    ↕    0    P    0    ↕

11 011 101
11 001 011
¬    d    ®
00 011 110

DD
CB

4

6

23

RR (IY + d)

↕    ↕    0    P    0    ↕

11 111 101
11 001 011
¬    d    ®
00 011 110

FD
CB

4

6

23

RLD

↕    ↕    0    P    0    •

11 101 101
01 101 111

ED
6F

2

5

18

RRD

↕    ↕    0    P    0    •

11 101 101
01 100 111

ED
67

2

5

18

SLA r

↕    ↕    0    P    0    ↕

11 001 011
00 100  r   

CB

2

2

8

r        Reg
000   B
001   C
010   D
011   E
100   H
101   L
111   A

SLA (HL)

↕    ↕    0    P    0    ↕

11 001 011
00 100 110

CB

2

4

15

SLA (IX + d)

↕    ↕    0    P    0    ↕

11 011 101
11 001 011
¬    d    ®
00 100 110

DD
CB

4

6

23

SLA (IY + d)

↕    ↕    0    P    0    ↕

11 111 101
11 001 011
¬    d    ®
00 100 110

FD
CB

4

6

23

SRA r

↕    ↕    0    P    0    ↕

11 001 011
00 101   r   

CB

2

2

8

SRA (HL)

↕    ↕    0    P    0    ↕

11 001 011
00 101 110

CB

2

4

15

SRA (IX + d)

↕    ↕    0    P    0    ↕

11 011 101
11 001 011
¬    d    ®
00 101 110

DD
CB

4

6

23

SRA (IY + d)

↕    ↕    0    P    0    ↕

11 111 101
11 001 011
¬    d    ®
00 101 110

FD
CB

4

6

23

SRL r

↕    ↕    0    P    0    ↕

11 001 011
00 111   r   

CB

2

2

8

SRL (HL)

↕    ↕    0    P    0    ↕

11 001 011
00 111 110

CB

2

4

15

SRL (IX + d)

↕    ↕    0    P    0    ↕

11 011 101
11 001 011
¬    d    ®
00 111 110

DD
CB

4

6

23

SRL (IY + d)

↕    ↕    0    P    0    ↕

11 111 101
11 001 011
¬    d    ®
00 111 110

FD
CB

4

6

23

Notes:

The P symbol in the P/V flag column indicates that the P/V flag contains the parity of the result.
r means any of the registers A, B, C, D, E, H, L.
CY means the carry flip-flop.

Flag Notation:

• = flag is not affected, 0 = flag is reset, 1 = flag is set,
↕ = flag is set according to the result of the operation.

Mnemonic

Symbolic
Operation

Flags
S    Z    H   P/V  N    C

Opcode
76 543 210

Hex

Bytes

M
Cycles

Clock
Cycles

Comments

BIT b, r

       __
Z ¬ r_b

X    ↕    1    X    0    •

11 001 011
01   b     r

CB

2

2

8

r        Reg
000   B
001   C
010   D
011   E
100   H
101   L
111   A

b       Bit
000   0
001   1
010   2
011   3
100   4
101   5
110   6
111   7

BIT b, (HL)

       ____
Z ¬ (HL)_b

X    ↕    1    X    0    •

11 001 011
01   b   110

CB

2

3

12

BIT b, (IX + d)

       ______
Z ¬ (IX+ d)_b

X    ↕    1    X    0    •

11 011 101
11 001 011
¬    d     ®
01   b   110

DD
CB

4

5

20

BIT b, (IY + d)

       ______
Z ¬ (IY+ d)_b

X    ↕    1    X    0    •

11 111 101
11 001 011
¬    d     ®
01   b   110

FD
CB

4

5

20

SET b, r

r_b ¬ 1

•     •     •     •     •     •

11 001 011
11   b     r

CB

2

2

8

SET b, (HL)

(HL)_b ¬ 1

•     •     •     •     •     •

11 001 011
11   b   110

CB

2

4

15

SET b, (IX + d)

(IX+ d)_b ¬ 1

•     •     •     •     •     •

11 011 101
11 001 011
¬    d     ®
11   b   110

DD
CB

4

6

23

SET b, (IY + d)

(IY+ d)_b ¬ 1

•     •     •     •     •     •

11 111 101
11 001 011
¬    d     ®
11   b   110

FD
CB

4

6

23

RES b, r

r_b ¬ 0

•     •     •     •     •     •

11 001 011
10   b     r

CB

2

2

8

RES b, (HL)

(HL)_b ¬ 0

•     •     •     •     •     •

11 001 011
10   b   110

CB

2

4

15

RES b, (IX + d)

(IX+ d)_b ¬ 0

•     •     •     •     •     •

11 011 101
11 001 011
¬    d     ®
10   b   110

DD
CB

4

6

23

RES b, (IY + d)

(IY+ d)_b ¬ 0

•     •     •     •     •     •

11 111 101
11 001 011
¬    d     ®
10   b   110

FD
CB

4

6

23

Notes:

The notation m_b indicates bit b (0 to 7) of location m.
BIT instructions are performed by an bitwise AND.

Flag Notation:

• = flag is not affected, 0 = flag is reset, 1 = flag is set, X = flag is “don’t care”,
↕ = flag is set according to the result of the operation.

Mnemonic

Symbolic
Operation

Flags
S    Z    H   P/V  N    C

Opcode
76 543 210

Hex

Bytes

M
Cycles

IN A, (n)

A ¬ (n)

•     •     •     •     •     •

11 011 011
¬    n     ®

DB

2

3

11

r        Reg
000   B
001   C
010   D
011   E
100   H
101   L
111   A

IN r, (C)

r ¬ (C)

↕    ↕    0    P    0    •

11 101 101
01   r    000

ED

2

3

12

OUT (n), A

(n) ¬ A

•     •     •     •     •     •

11 010 011
¬    n     ®

D3

2

3

11

OUT (C), r

(C) ¬ r

•     •     •     •     •     •

11 101 101
01   r    001

ED

2

3

12

Notes:

The V symbol in the P/V flag column indicates that the P/V flag contains the overflow of the operation.
Similarly the P symbol indicates parity.
r  means any of the registers A, B, C, D, E, H, L.

Flag Notation:

• = flag is not affected, 0 = flag is reset, 1 = flag is set,
↕ = flag is set according to the result of the operation.