The Cnt8 component is a synchronous binary counter, 8-bits, up/down, presettable, with enable. A test circuit, using the counter, is visible in the next figure. Click on the figure to open the schematic in the d-DcS:

The clock input: Ck

Ck is the clock input: it synchronizes the count operations.

The clear input: !CL

When low (active), !CL sets to zero the outputs Q7..Q0, in an asynchronous mode. If !CL is active, all the other inputs, included the clock CK, are disabled (the clear input is prioritary).

The load input: LD

When high (active), LD stores the value set on the inputs P7..P0 on the outputs Q7..Q0, in a synchronous mode, on the clock positive edge.

The enable inputs: En, Et

If !CL and LD are not active, the counter is ready to count, according to other inputs En (Enable Count), Et (Enable Terminal Count) and U/!D (Up/Down). En and Et are active high and work in synchronous mode: when En or Et is set to low, the count is inhibited; when En = Et = high, the count is enabled and executed on the clock positive edge. Moreover, Et, when is high, enables the output Tc (Terminal Count).

The direction input: U/!D

The input U/!D (=Up/!Down) works in synchronous mode and defines the count direction: when it is set to high, the count on the outputs Q7..Q0 goes Up (increases); when it is set to low, the count goes Down (decreases).

The counter outputs: Q7 .. Q0

The eight counter outputs Q7..Q0 show the count value. The count is cyclic, in natural binary, from '00000000' (0) to '11111111' (255), or vice versa, according to the direction set by the U/!D input.

The "Terminal Count" output: Tc

The "Terminal Count" output Tc is active high and is a combinational function of the value of the outputs Q7..Q0, the direction input U/!D and the enable input Et. Tc is active if the count value has reached its terminal value. When U/!D sets the Up direction, Tc is active if Q7..Q0 = '11111111' and Et = high; if U/!D sets the Down direction, Tc is active when Q7..Q0 = '00000000' and Et = high. When Et is low, the output Tc is always low.

The test circuit

In the given d-DcS file, some suitable test sequences are available in the timing diagram window.