The counter Cnt4 is a library component available in the d-DcS. Click on the figure to open, in the d-DcS, the following test circuit:

The Cnt4 component is a synchronous 4-bits binary counter, module 16, Up/Down, Presettable.

Q3, Q2, Q1, Q0 are the outputs of the counter (Q3 = MSB, Q0 = LSB).

The clear input CL is asynchronous: when it is active (CL=0) the outputs Q3..Q0 are forced to zero, with no regards for the other control and clock inputs.

The load input LD is synchronous: when CL is inactive and LD is active (LD = '1'), the inputs P3..P0 are copied to the outputs Q3..Q0, on the rising edge of the clock input CK (when LD is active, the other inputs En, Et and Up are ignored).

The enable inputs En ('Enable Count'), Et ('Enable Terminal Count') and the direction input Up are synchronous, and control the counter functionality. When CL and LD are inactive, even if only one between En and Et is inactive, counting is inhibited. When CL and LD are inactive, and En and Et are both active (= '1'), at every rising edge of the clock CK, the Q3..Q0 value is incremented by one if the input U/D is high, or decremented by one if the input U/D is low.

If Et is set active, the output Tc ('Terminal Count') is activated when the counter outputs Q3..Q0 have the maximum value of '1111' (if the count is set forward), or when the outputs Q3..Q0 have the minimum value '0000' (if the count is set backward); when Et is set to '0', instead, Tc is always '0'.

When counting is enabled (En = Et = '1'), the function of Tc is always enabled. In the remaining combinations of En and Et, counting is disabled, but the function of Tc can also be enabled with the combination En = '0', Et = '1'.

You are requested to test the behaviour of the counter, using the d-DcS timing simulation . In the following figure we suggest a suitable input timing sequence for the simulation (defined in the timing diagram window), although it can be useful to 'explore' other interesting combinations of input signals sequences: