The following synchronous sequential network is a module-4 Johnson counter. It is based on a two-stages Shift Register, with the last bit returned, inverted, to the first stage input. Click on the figure to open the schematic in the d-DcS:

Then, verify the network behaviour with the timing simulator . A simple test sequence is available in the Timing Diagram window: study, first, the count sequence observed on the outputs FC (MSB) and FB (LSB). Which binary code the sequence represents?

Next, consider the four waveforms the outputs (FA, FB, FC and FD). The particulare time relation among the four waveforms permits to use this circuit to generate polyphase clock signals, i.e. shifted in a regular mode (in this case, by a 1/4 of the clock period).