The following circuit is a 3-bits "shift-register", based on 'E-PET' flip-flops. Click on the figure to open in the d-DcS a trace of the network's schematic, and then complete it:

Once completed the schematic, using the timing simulation , verify the correct flow of the information throught the register, given a suitable data input waveform (a suitable test sequence is available in the Timing Diagram window, including the !Reset activation).

Next, let us consider the 3 bits QaQbQc as a signed two’s complement coded number (Qa = sign). Define a Data input sequence such that the circuit produces the sequence below (represented in decimal):

0, -4, -2, +3, +1, 0.

Write the Data input sequence in a table as the following one. In the table you specify the Data input values (on the left hand side) and the resulting values (expressed in binary and decimal format) on the output Qa, Qb and Qc (on the right side, after the symbol representing the clock event).