Open the following circuit in the d-DcS, with a click on the figure:

This is a combinational network with three inputs C, B, A and an output U, implemented with a multiplexer 8-1. Using the functional simulation , compile a K-map describing the network.

What kind of logic function this circuit performs? Could it be used to check the parity of the input bits?

Using the same structural approach, modify the previous circuit to implement the following Boolean function [note: !C = not(C)]:

U = (!C and B) or (C and !B and A) or (B and !A)

Start with the truth table of the given Boolean function, then modify the network to implement it. Click here to open the schematic to be completed. Verify the circuit behaviour through a timing simulation (a suitable test sequence is available in the Timing Diagram window).