The serial line receiver will expect a signal, from the line LINE_IN, as the one described in the following figure:

The 10 bit packet is composed as follows:

1. One start bit (high);
2. 8 data bits, D7..D0 (D0 ahead);
3. One stop bit (low);
4. Bit/rate = 62500 bits per second (bit time = 16 µS). The receiver clock frequency is 1 MHz.

The next figure shows the receiver, based on a Finite State Machine as controller (click on the figure to open the schematic in the d-DcS editor):

The system is composed of a Bit Time Counter, a Shift Register, a Bit Counter, and a Controller.

Bit Time Counter
The Bit Time Counter, based on the Cnt4 component, is in charge of dividing by 16 the frequency of RX_CK (1 MHz), in order to receive the data bits at the given bit/rate (62500 b/s = 1 MHz /16): this part of a serial receiver is usually named Baud Rate Generator. The counter is set up to count down cyclically; every time the outputs Q3..Q0 reach the number '0000', the output TC (terminal count) is activated, resulting in a pulse every 16 clock cycles. The cyclic activation of TC is used by the Controller to synchronize the sampling of each data bit at the given bit rate. LD signal presets the counter to the value '0110' (inputs P3..P0), as described in the following.

 Shift Register
The Shift Register (the Univ8 component) de-serializes the data packets, incoming from LINE_IN, on the output lines RXBYTE. S1 and S0 control the register mode of operation: when the Controller drives S1 = S0 = '0', the register state will not change. Serial data input (InR) is connected directly to the LINE_IN. Data input and shifting occurs when the Controller drives S1 = '0' and S0 = '1'. The shift register, at the end of the receiving operations, will make parallel data available to the outputs RXBYTE.

 Bit Counter
The Bit Counter (also based on a Cnt4) counts the number of bits to be received. The Controller initializes the counter to '1000', setting the LD line. Every time the Controller activates the EN line, the count is decremented by one. Checking the counter terminal count (TC), the Controller will know when no more data bits need to be received.

 Controller
The Controller functionality is described by the following ASM chart (click on it to open the FSM file in the d-FsM):

The controller clock frequency is 16 times the bit rate of the received packet. To catch the Start Bit, the controller samples its input LIN (alias LINE_IN) at every positive clock edge, in state (a). When LIN goes high, the controller continues to sample it, at the same rate, in state (b). If LIN is sampled always high, until the middle of the bit time is reached, the controller declares valid the Start Bit, and goes in state (c). On the contrary, if LIN returns to low, operations are restarted, looking again for a next valid start bit, in state (a).

Note that the middle of the bit time is signaled by the TCB line, that is generated by the Bit Time Counter. This one is initialized, by means of the LD line, in state (a), to the starting value '0110'. As a result of this initialization, the first occurrence of TCB is generated on the middle of the bit time; the next occurrences, instead, will be generated every bit time (i.e. every 16 clock cycles, the counter module).

The controller checks TCB also in state (c), to synchronize the operations of the Shift Register. When TCB goes high, the controller sets S0 = '1' and S1 = '0', in state (d), causing the LINE_IN data acquisition (on InR of the Univ8 component) and the right shift of all the other bits of the register. This couple of states (c,d) is repeated 8 times, i.e. until TCN is activated.

TCN is generated by the Bit Counter when it reaches '0000', i.e. when the received data bits are over. Note that the Bit Counter is decremented, by means of EN, in state (d), each time a bit is acquired in the shift register.

The next task of the algorithm relates to the Stop Bit validation. In state (c), when TCB is activated, but all the data bits have been received (TCN = '1'), instead of acquiring the Stop Bit in the shift register, the controller checks directly its value. If the Stop Bit is zero, the packet is assumed valid, and the RDY signal generated, in state (e), for the duration of a bit time. Otherwise, if the Stop Bit is high, the received data bits will be ignored (because the RDY signal is not generated) and the algorithm will re-start from state (a). The loop state (f) is a simple attempt to recover the error state due to the wrong stop bit. In state (f) the controller waits for a low value on LIN, before to catch the next start bit (although this solution couldn't be the better one to handle a wrong stop bit reception).

You can test the circuit using the d-DcS simulator, in Animation Mode and in Timing Mode . A proper test sequence is available in the timing simulation window.