Deeds - Design of a programmable generator of periodic sequences [050330]

Design of FSM-controlled digital systems

Giuliano Donzellini, Domenico Ponta

Design of a programmable generator of periodic sequences

v1.80

The purpose of this lab is to design a programmable multiphase square-wave generator. It generates three cyclic signals, UA, UB and UC, accordingly to the following timing diagram:

UA, UB and UC outputs timing diagram

The durations at high level TA, TB, and TC of each signal are independently programmable. The architecture of the system is described in the following figure:

Architecture of the programmable sequences generator

All the modules are synchronous with the master clock CK. The MSF generates the requested signals UA, UB and UC. The three timer modules are in charge of setting the time duration of each output signal, and are driven by the control FSM. Before the FSM starts generating each of the output signals (UA, UB or UC), the FSM presets the corresponding timer (Timer TA, Timer TB or Timer TC). Next, the FSM generates that signal until the assigned time elapses. Then, the FSM activates the next output, repeating the same operations as before.

Each timer is designed around a programmable counter, using the Cnt4 (available in the component library of the d-DcS). In the following figure a possible solution for the timer (a click on the figure will open this circuit in the d-DcS, to test it stand-alone):

The counter is always enabled (En = Et = '1'), the direction U/!D is preset to down, the clear (!CL) is available to reset the counter. The LD signal presets the counter to the value defined by the P3..P0 switches. When LD is released, the counter starts to count down until it generates the TC (terminal count) signal (the four-LED display is useful to observe the counting progress).

Consider the following schematic, using three Cnt4 counter components. Click on the figure to open the circuit (to be completed) in the d-DcS:

To complete the system schematic, design the control FSM, following the given specifications (here a trace for the ASM chart).

Last, perform some d-DcS timing simulations representing, in separate sheets, two or more different setup configurations. Describe, for your particular solution, the functional relation between between the number set on the switches and the time duration of the output signals.