Given the following combinational network (click on the figure to open the schematic in the d-DcS).

Compile a truth table of the network. Then, just by looking at the table, design a simpler logic network with the same behavior (click here to open, in the d-DcS, the schematic to be completed). Verify the equivalence of the two networks, using the Timing Diagram Simulation . Show their behavior for all the combinations of A and B inputs (suitable test sequences are available in the Timing Diagram window).

Last, re-design the network using a 4-1 multiplexer (MUX 4 -1), completing the connections highlighted in the following schematic (click on the figure to open it in the d-DcS):

Execute a timing simulation , showing the results for all the combinations of A and B inputs (as before, a suitable test sequence is available in the Timing Diagram window).