Load the following circuit in the d-DcS,
with a click on the figure:

Using the functional
simulation , compile a truth table with the results of
the functional simulation.
Then, with the timing simulation , show its behavior for all the combinations of input values. A suitable test sequence is available in the Timing Diagram window.
This circuit is a "decoder":
- What is the role of S1 and S0?
- What is the role of EN?
- What is the relation between the number of inputs and the number of outputs?
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