Introduction to digital electronics

Giuliano Donzellini, Domenico Ponta

Analysis of simple logic gates

001002

 

v1.71

This exercise introduces you to combinational logic networks. If you click on the figure below, representing a simple logic network, you'll open in the d-DcS a sort of template of the network:

Next step is to complete the schematic, to obtain the same network of the figure. You will start the functional simulation (Interactive Animation) of the network by clicking, on the d-DcS tooolbar, the command . Now the two input switches can be toggled and the gates' output values will change accordingly. At this point, we suggest that you draw the truth table for each output and then fill the output columns with the data resulting from the simulation.

Last task requested is the timing simulation of the same network (Timing Diagram Simulation) . You start the timing simulation of the network by clicking, on the d-DcS tooolbar, the command . The input values must be drawn directly on the timing diagram window. You should define the values versus time of the two inputs, such as all the possible combinations of A and B are tested.