Mnemonic

Symbolic
Operation

Flags
S    Z    H   P/V  N    C

Opcode
76 543 210

Hex

Bytes

M
Cycles

Clock
Cycles

Comments

ADD HL, ss

HL ¬ HL + ss

•     •     ↕²   •     0    ↕¹

00 ss1 001

1

3

11

ss     Reg.
00     BC
01     DE
10     HL
11     SP

pp     Reg.
00     BC
01     DE
10        IX
11        SP

rr      Reg.
00     BC
01        DE
10     IY
11     SP

ADC HL, ss

HL ¬ HL + ss + CY

↕¹   ↕¹   ↕²   V¹  0    ↕¹

11 101 101
01 ss1 010

ED

2

4

15

SBC HL, ss

HL ¬ HL – ss –  CY

↕¹   ↕¹   ↕²   V¹  1    ↕¹

11 101 101
01 ss0 010

ED

2

4

15

ADD IX, pp

IX ¬ IX + pp

•     •     ↕²   •     0    ↕¹

11 011 101
00 pp1 001

DD

2

4

15

ADD IY, rr

IY ¬ IY + rr

•     •     ↕²   •     0    ↕¹

11 111 101
00  rr1  001

FD

2

4

15

INC ss

ss ¬ ss + 1

•     •     •     •     •     •

00 ss0 011

1

1

6

INC IX

IX ¬ IX + 1

•     •     •     •     •     •

11 011 101
00 100 011

DD
23

2

2

10

INC IY

IY ¬ IY + 1

•     •     •     •     •     •

11 111 101
00 100 011

FD
23

2

2

10

DEC ss

ss ¬ ss - 1

•     •     •     •     •     •

00 ss1 011

1

1

6

DEC IX

IX ¬ IX - 1

•     •     •     •     •     •

11 011 101
00 101 011

DD
2B

2

2

10

DEC IY

IY ¬ IY - 1

•     •     •     •     •     •

11 111 101
00 101 011

FD
2B

2

2

10

Notes:

The V symbol in the P/V flag column indicates that the P/V flag contains the overflow of the operation.
Ss means any of the registers BC, DE, HL, SP.
Pp means any of the registers BC, DE, IX, SP.
Rr means any of the registers BC, DE, IY, SP.
16 bit additions are performed by first adding the two low order eight bits, and then the two high order eight bits.
¹  Indicates the flag is affected by the 16 bit result of the operation.
²  Indicates the flag is affected by the 8 bit addition of the high order eight bits.
CY means the carry flip-flop.

Flag Notation:

• = flag is not affected, 0 = flag is reset, 1 = flag is set,
↕ = flag is set according to the result of the operation.